1. Field of the Invention
The present invention relates to a three dimensional stacked nonvolatile semiconductor memory.
2. Description of the Related Art
BiCS (Bit Cost Scalable) technology is known as a technology for suppressing a bit cost of a semiconductor memory by increasing the capacity thereof by a three dimensional structure (refer to, for example, “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory” 2007 Symposium on VLSI Technology Digest of Technical Papers. p. 14).
A nonvolatile semiconductor memory to which the BiCS technology is applied (hereinafter, called a BiCS memory) has a feature in that it not only has a three dimensional structure but makes bit cost scalability possible so that a bit cost can be reduced in proportion to an increase of the number of stacked layers by devising a device structure and a process technology.
In, for example, a NAND flash memory to which the BiCS technology is applied (hereinafter, called a BiCS-NAND flash memory), a memory capacity, which greatly exceeds the limit of the memory capacity of a NAND flash memory having a two-dimensional structure, can be realized by increasing the number of cells in a longitudinal direction which comprise a NAND column by increasing the number of stacked layers.
However, since the BiCS memory which is represented by a BiCS-NAND flash memory has a unique device structure, there are many problems to be solved to practically use the BiCS memory.
An unstable potential of a source diffusion layer is exemplified as one of the problems.
In the BiCS memory, a cell unit comprising a memory cell array is formed on side surfaces of columnar semiconductors extending in a direction longitudinal to a semiconductor substrate. Accordingly, a source diffusion layer, which is common to blocks, is formed in the semiconductor substrate just under the blocks. Since it is difficult to dispose a contact area of the source diffusion layer in the memory cell array, the contact area is ordinarily formed outside of the memory cell array to connect the source diffusion layer to a source line.
However, in this case, since the contact area is formed outside of the memory cell array, a phenomenon such as floating of a source potential and the like is generated in the source diffusion layer by the resistance of the source diffusion layer, which makes it difficult to stabilize the potential of the source diffusion layer. Thus, the phenomenon acts as an unstable factor in, for example, a read operation.